Li Zhou, Hao Wen, Radu Teodorescu, David H.C. Du, Distributing Deep Neural Networks with Containerized Partitions at the Edge. HotEdge '19 Workshop at 2019 USENIX Annual Technical Conference [pdf]
Timothy Miller, Renji Thomas and Radu Teodorescu, Mitigating the Effects of Process Variation in Ultra-low Voltage Chip Multiprocessors using Dual Supply Voltages and Half-Speed Stages, Workshop on Energy-Efficient Design, in conjunction with ISCA, June 2011
Timothy Miller, Nagarjuna Surapaneni, Radu Teodorescu and Joanne Degroat, Flexible Redundancy in Robust Processor Architecture, Workshop on Energy-Efficient Design (WEED), in conjunction with ISCA, June 2009
Radu Teodorescu, Brian Greskamp, Jun Nakano, Smruti R. Sarangi, Abhishek Tiwari and Josep Torrellas, VARIUS: A Model of Parameter Variation and Resulting Timing Errors for Microarchitects, Workshop on Architectural Support for Gigascale Integration (ASGI), in conjunction with ISCA, June 2007 [pdf]
S. Chen, B. Falsafi, P. B. Gibbons, M. Kozuch, T. C. Mowry, R. Teodorescu, A. Ailamaki, L. Fix, G. R. Ganger, B. Lin, S. W. Schlosser, Log-Based Architectures for Continuous Monitoring of Deployed Code, Workshop on Architectural and System Support for Improving Software Dependability (ASID), in conjunction with ASPLOS, October 2006 [pdf]
Radu Teodorescu and Josep Torrellas, Empowering Software Debugging Through Architectural Support for Program Rollback, Workshop on the Evaluation of Software Defect Detection Tools, in conjunction with PLDI 2005, Chicago, June 2005 [pdf]
Radu Teodorescu and Josep Torrellas, The Design Complexity of Program Undo Support in a General-Purpose Processor, Workshop on Complexity-Effective Design, in conjunction with ISCA 2005, Madison, Wisconsin, June 2005 [pdf]
Radu Teodorescu and Josep Torrellas, Prototyping Architectural Support for Program Rollback: An Application to Software Debugging, Workshop on Architecture Research Using FPGA Platforms, in conjunction with HPCA-11, San Francisco, February 2005 [abstract]