Moein Ghaniyoun, Kristin Barber, Yuan Xiao, Yinqian Zhang, and Radu Teodorescu, TEESec: Pre-Silicon Vulnerability Discovery for Trusted Execution Environments, 50th Annual International Symposium on Computer Architecture (ISCA), June 17–21, 2023 [pdf]
Jiuqin Zhou, Yuan Xiao, Radu Teodorescu, Yinqian Zhang, ENCLYZER: Automated Analysis of Transient Data Leaks on Intel SGX, 2022 IEEE International Symposium on Secure and Private Execution Environment Design (SEED), September 2022 [pdf]
Mengyuan Li, Luca Wilke , Jan Wichelmann, Thomas Eisenbarth, Radu Teodorescu, Yinqian Zhang, A Systematic Look at Ciphertext Side Channels on AMD SEV-SNP, 43rd IEEE Symposium on Security and Privacy (S&P), May 2022 [pdf]
Saikat Majumdar, Mohammad Hossein Samavatian, Radu Teodorescu, Characterizing Side-Channel Leakage of DNN Classifiers though Performance Counters, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), June 2022 [pdf]
Kristin Barber, Moein Ghaniyoun, Yinqian Zhang and Radu Teodorescu, A Pre-Silicon Approach to Discovering Microarchitectural Vulnerabilities in Security Critical Applications, IEEE Computer Architecture Letters (CAL), vol. 01, pp. 9-12, January 2022. [pdf] Best of CAL 2022
Saikat Majumdar, Mohammad Hossein Samavatian, Kristin Barber, Radu Teodorescu, Using Undervolting as an On-Device Defense Against Adversarial Machine Learning Attacks, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), December 2021 [pdf]
Moein Ghaniyoun, Kristin Barber, Yinqian Zhang, Radu Teodorescu, IntroSpectre: A Pre-Silicon Framework for Discovery and Analysis of Transient Execution Vulnerabilities, International Symposium on Computer Architecture (ISCA), June 2021 [pdf][slides][video]
Jia Guo, Gagan Agrawal, Radu Teodorescu, Fused DSConv: Optimizing Sparse CNN Inference for Execution on Edge Devices. IEEE/ACM International Symposium on Cluster, Cloud and Internet Computing, (CCGrid), May 2021 [pdf]
Mohammad Samavatian, Anys Bacha, Li Zhou, Radu Teodorescu, RNNFast: An Accelerator for Recurrent Neural Networks Using Domain Wall Memory, ACM Journal on Emerging Technologies in Computing Systems, (JETC) 2020 [pdf]
Jia Guo, Radu Teodorescu, Gagan Agrawal, A Pattern-Based API for Mapping Applications to a Hierarchy of Multi-Core Devices, IEEE/ACM International Symposium on Cluster, Cloud and Internet Computing (CCGrid), May 2020 [pdf]
Yuan Xiao, Yinqian Zhang, Radu Teodorescu, SPEECHMINER: A Framework for Investigating and Measuring Speculative Execution Vulnerabilities, Network and Distributed System Security Symposium (NDSS), 2020 [pdf/slides/talk]
Li Zhou, Mohammad Samavatian, Anys Bacha, Saikat Majumdar, Radu Teodorescu, Adaptive parallel execution of deep neural networks on heterogeneous edge devices. ACM/IEEE Symposium on Edge Computing, (SEC), 2019 [pdf]
Kristin Barber, Anys Bacha, Li Zhou, Yinqian Zhang, Radu Teodorescu, SpecShield: Shielding Speculative Data from Microarchitectural Covert Channels, International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2019 [pdf] MICRO Top Picks 2019 honorable mention
Kristin Barber, Anys Bacha, Li Zhou, Yinqian Zhang, Radu Teodorescu, Isolating Speculative Data to Prevent Transient Execution Attacks, Computer Architecture Letters (CAL), 2019 [pdf] Best of CAL 2019
Li Zhou, Ren Chen, Yinglong Xia, Radu Teodorescu, C-Graph: A highly efficient concurrent graph reachability query framework, International Conference on Parallel Processing (ICPP), 2018 [pdf]
Xiang Pan, Anys Bacha, Spencer Rudolph, Li Zhou, Yinqian Zhang, Radu Teodorescu, NVCool: When Non-Volatile Caches Meet Cold Boot Attacks, IEEE International Conference on Computer Design (ICCD), 2018 [pdf]
Xiang Pan, Anys Bacha and Radu Teodorescu, Respin: Rethinking Near-Threshold Multiprocessor Design with Non-Volatile Memory, IEEE International Parallel & Distributed Processing Symposium (IPDPS), May 2017 [pdf]
Venmugil Elango, Naser Sedaghati, Fabrice Rastello, Louis-Noel Pouchet, J. Ramanujam, Radu Teodorescu,P. Sadayappan, On Using the Roofline Model with Lower Bounds on Data Movement, HiPEAC, European Network on High-performance Embedded Architecture and Compilation, 2017 [pdf]
Dimitrios Skarlatos, Renji Thomas, Aditya Agrawal, Shibin Qin, Robert Pilawa, Ulya Karpuzcu, Radu Teodorescu, Nam Sung Kim, Josep Torrellas, Snatch: Opportunistically Reassigning Power Allocation between Processor and Memory in 3D Stacks, International Symposium on Microarchitecture (MICRO), October 2016 [pdf]
Yuan Xiao, Xiaokuan Zhang, Yinqian Zhang, Radu Teodorescu, One Bit Flips, One Cloud Flops: Cross-VM Row Hammer Attacks and Privilege Escalation, USENIX Security'16, August 2016 [pdf]
Renji Thomas, Naser Sedaghati, Radu Teodorescu, EmerGPU: Understanding and Mitigating Resonance-Induced Voltage Noise in GPU Architectures, International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2016 [pdf]
Renji Thomas, Kristin Barber, Naser Sedaghati, Li Zhou, Radu Teodorescu, Core Tunneling: Variation-Aware Voltage Noise Mitigation in GPUs, International Symposium on High-Performance Computer Architecture (HPCA), March 2016 [pdf] nominated for Best Paper Award
Anys Bacha and Radu Teodorescu, Authenticache: Harnessing Cache ECC for System Authentication, International Symposium on Microarchitecture (MICRO), December 2015 [pdf] MICRO Top Picks 2015 honorable mention
Anys Bacha and Radu Teodorescu, Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors, International Symposium on Microarchitecture (MICRO), December 2014 [pdf]
Xiang Pan and Radu Teodorescu, NVSleep: Using Non-Volatile Memory to Enable Fast Sleep/Wakeup of Idle Cores, IEEE International Conference on Computer Design (ICCD), October 2014 [pdf]
Anys Bacha and Radu Teodorescu, Dynamic Reduction of Voltage Margins by Leveraging On-chip ECC in Itanium II Processors, International Symposium on Computer Architecture (ISCA), June 2013 [pdf]
Timothy N. Miller, Renji Thomas, Xiang Pan, Radu Teodorescu, VRSync: Characterizing and Eliminating Synchronization-Induced Voltage Emergencies in Many-core Processors, International Symposium on Computer Architecture (ISCA), June 2012 [pdf]
Timothy Miller, Nagarjuna Surapaneni, Radu Teodorescu, Runtime failure rate targeting for energy-efficient reliability in chip microprocessors, Concurrency and Computation: Practice and Experience (CCPE), July 2012 [pdf]
Timothy N. Miller, Xiang Pan, Renji Thomas, Naser Sedaghati, Radu Teodorescu, Booster: Reactive Core Acceleration for Mitigating the Effects of Process Variation and Application Imbalance in Low-Voltage Chips, International Symposium on High-Performance Computer Architecture (HPCA), February 2012 [pdf]
Timothy Miller, Renji Thomas and Radu Teodorescu, Mitigating the Effects of Process Variation in Ultra-low Voltage Chip Multiprocessors using Dual Supply Voltages and Half-Speed Units, IEEE Computer Architecture Letters (CAL), 2012 [pdf]
Naser Sedaghati, Renji Thomas, Louis-Noel Pouchet, Radu Teodorescu, P. Sadayappan, StVEC: A Vector Instruction Extension for High Performance Stencil Computation, International Conference on Parallel Architectures and Compilation Techniques (PACT), October 2011 [pdf]
Timothy Miller, James Dinan, Renji Thomas, Bruce Adcock and Radu Teodorescu, Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches, International Symposium on Microarchitecture (MICRO), December 2010 [pdf]
Timothy Miller, Nagarjuna Surapaneni and Radu Teodorescu, Flexible Error Protection for Energy Efficient Reliable Architectures, International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Petrópolis, Brazil, October 2010 [pdf]
Radu Teodorescu and Josep Torrellas, Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors, 35th International Symposium on Computer Architecture (ISCA), June 2008 [pdf]
Smruti R. Sarangi, Brian Greskamp, Radu Teodorescu, Jun Nakano, Abhishek Tiwari and Josep Torrellas, VARIUS: A Model of Parameter Variation and Resulting Timing Errors for Microarchitects, IEEE Transactions on Semiconductor Manufacturing (IEEE TSM), February 2008 [pdf]
Radu Teodorescu, Jun Nakano, Abhishek Tiwari and Josep Torrellas, Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing, 40th International Symposium on Microarchitecture (MICRO), December 2007 [pdf]
Pin Zhou, Radu Teodorescu and Yuanyuan Zhou, HARD: Hardware-Assisted Lockset-based Race Detection, IEEE International Symposium on High-Performance Computer Architecture (HPCA), February 2007 [pdf]
Radu Teodorescu, Jun Nakano, Josep Torrellas, SWICH: A Prototype for Efficient Cache-Level Checkpointing and Rollback, IEEE Micro, vol. 26, Sept/Oct, 2006 [pdf]
Radu Teodorescu and Josep Torrellas, Prototyping Architectural Support for Program Rollback Using FPGAs, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), April 2005 [pdf]
Nedevschi, S., Teodorescu, R., Gyongyi, Z., Nedevschi, S., Jr., Leuca, A. and Olinic, D., Integrated Medical Imaging Environment, International Conference on Automation, Quality, and Testing, Robotics, May 2002
Nedevschi, S., Gyongyi, Z., Teodorescu, R., Nedevschi, S., Jr. and Olinic, D., Distributed system for medical image acquisition, processing, storage, and retrieval, First RoEduNet Conference, April 2002
Nedevschi, S., Salomie, I., Gyongyi, Z., Teodorescu, R., Nedevschi, S., Jr. and Olinic, D., Retrieval of DICOM ultrasound images based on structured medical description, International Conference on Emerging Telecommunications Technologies and Applications, October 2001
Nedevschi, S., Gyongyi, Z., Teodorescu, R., Nedevschi, S., Jr. and Olinic, D., E-environment for medical image processing, Electronic Business on the Internet, October 2001
Nedevschi, S., Olinic, D., Gyongyi, Z., Teodorescu, R. and Nedevschi, S., Jr., Feature based retrieval of echocardiographic images using DICOM structured reporting, IEEE Computers in Cardiology, September 2001