The Computer Architecture Research Lab at Ohio State University is focused on developing the next generation energy efficient multicore architectures that meet the challenges of increasingly unreliable technology. More details on our research are available here.
01/20/2016 Our new paper on voltage noise, EmerGPU: Understanding and Mitigating Resonance-Induced Voltage Noise in GPU Architectures, was accepted at ISPASS 2016.
11/24/2015 Congratulations to Dr. Renji Thomas on his brand new PhD and good luck on his new career at Intel!
11/20/2015 Our paper Core Tunneling: Variation-Aware Voltage Noise Mitigation in GPUs was accepted at HPCA 2016 and was nominated for the Best Paper Award. Congratulations Renji and team!
10/15/2015 Congratulations to Dr. Naser Sedaghati on his new PhD and new job at Imagination Technologies!
9/05/2015 Our paper “Authenticache: Harnessing Cache ECC for System Authentication” was accepted at MICRO 2015! Aloha!?
9/01/2014 Radu was promoted to Associate Professor.
4/14/2014 Our alumnus, Timothy Miller, PhD ’12, new professor at Binghamton University, was recently awarded the Faculty Early Career Development (CAREER) award. This award supports junior faculty who exemplify the role of teacher-scholars through outstanding research, excellent education and the integration of education and research. Many congratulations Tim!
- *new* EmerGPU: Understanding and Mitigating Resonance-Induced Voltage Noise in GPU Architectures, International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2016
- *new* Core Tunneling: Variation-Aware Voltage Noise Mitigation in GPUs, International Symposium on High-Performance Computer Architecture (HPCA), March 2016, nominated for Best Paper Award
- *new* Authenticache: Harnessing Cache ECC for System Authentication, International Symposium on Microarchitecture (MICRO), December 2015, MICRO Top Picks 2015 honorable mention
- Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors, International Symposium on Microarchitecture (MICRO), December 2014
- NVSleep: Using Non-Volatile Memory to Enable Fast Sleep/Wakeup of Idle Cores, IEEE International Conference on Computer Design (ICCD), October 2014
- Dynamic Reduction of Voltage Margins by Leveraging On-chip ECC in Itanium II Processors, International Symposium on Computer Architecture (ISCA), June 2013
- VRSync: Characterizing and Eliminating Synchronization-Induced Voltage Emergencies in Many-core Processors, International Symposium on Computer Architecture (ISCA), June 2012
- Booster: Reactive Core Acceleration for Mitigating the Effects of Process Variation and Application Imbalance in Low-Voltage Chips, International Symposium on High-Performance Computer Architecture (HPCA), February 2012
- Mitigating the Effects of Process Variation in Ultra-low Voltage Chip Multiprocessors using Dual Supply Voltages and Half-Speed Units, IEEE Computer Architecture Letters (CAL), 2012
- Runtime failure rate targeting for energy-efficient reliability in chip microprocessors, Concurrency and Computation: Practice and Experience (CCPE), July 2012
- StVEC: A Vector Instruction Extension for High Performance Stencil Computation, International Conference on Parallel Architectures and Compilation Techniques (PACT), October 2011
- Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches, International Symposium on Microarchitecture (MICRO), December 2010
- Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors, International Symposium on Computer Architecture (ISCA), June 2008
- VARIUS: A Model of Parameter Variation and Resulting Timing Errors for Microarchitects, IEEE Transactions on Semiconductor Manufacturing (IEEE TSM), February 2008