I am an Associate Professor in the Department of Computer Science and Engineering at Ohio State University. I lead the Architecture Research Lab. Our research interests include computer architecture, nanoscale technology scaling, reliability, variability and power management. I received my Ph.D. from the Department of Computer Science, University of Illinois at Urbana-Champaign where I was a member of the IACOMA group working with Prof. Josep Torrellas. I was the recipient of a Lumley Award in 2014, an NSF CAREER award in 2012, Intel Foundation Fellowship for 2007-2008 and the W. J. Poppelbaum Award for 2008.
A high-level summary of my research has been published recently in the Spring 2013 CSE Newsletter. For more details and research updates please visit my group’s website.
My NSF CAREER award titled An Integrated Treatment of Voltage Noise and Process Variability in Many-core and GPU Systems with Microarchitectural Solutions was featured on a College of Engineering announcement with a brief overview.
I am looking for very bright and motivated students to join my research group. If you are interested in working with us send me an email or drop by my office.
- *new*Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors, International Symposium on Microarchitecture (MICRO), December 2014
- *new*NVSleep: Using Non-Volatile Memory to Enable Fast Sleep/Wakeup of Idle Cores, IEEE International Conference on Computer Design (ICCD), October 2014
- Dynamic Reduction of Voltage Margins by Leveraging On-chip ECC in Itanium II Processors, International Symposium on Computer Architecture (ISCA), June 2013
- VRSync: Characterizing and Eliminating Synchronization-Induced Voltage Emergencies in Many-core Processors, International Symposium on Computer Architecture (ISCA), June 2012
- Booster: Reactive Core Acceleration for Mitigating the Effects of Process Variation and Application Imbalance in Low-Voltage Chips, International Symposium on High-Performance Computer Architecture (HPCA), February 2012
- Mitigating the Effects of Process Variation in Ultra-low Voltage Chip Multiprocessors using Dual Supply Voltages and Half-Speed Units, IEEE Computer Architecture Letters (CAL), 2012
- StVEC: A Vector Instruction Extension for High Performance Stencil Computation, International Conference on Parallel Architectures and Compilation Techniques (PACT), October 2011
- Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches, International Symposium on Microarchitecture (MICRO), December 2010
- Flexible Error Protection for Energy Efficient Reliable Architectures, International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Petrópolis, Brazil, October 2010
- Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors, International Symposium on Computer Architecture (ISCA), June 2008
- VARIUS: A Model of Parameter Variation and Resulting Timing Errors for Microarchitects, IEEE Transactions on Semiconductor Manufacturing (IEEE TSM), February 2008
- Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing, International Symposium on Microarchitecture (MICRO), December 2007
- HARD: Hardware-Assisted Lockset-based Race Detection, International Symposium on High-Performance Computer Architecture (HPCA), February 2007
CSE775 and CSE675
CSE888 - Readings in Computer Architecture
I helped organize the Workshop on Near-threshold Computing (WNTC) held in conjunction with the International Symposium on Microarchitecture (MICRO) 2012, Vancouver, Canada. Details on the WNTC website.
MICRO 2011, Program Committe Member
ICPP 2010, Program Committe Member
SBAC-PAD 2010, Program Committee Member
SBAC-PAD 2009, Program Committee Member
HiPC 2009, Program Committee Member
I was born in Cluj-Napoca, in the beautiful province of Transilvania in Romania. I received an Engineer Diploma from the Technical University of Cluj-Napoca in 2002.