VLSI design methodology; specification of VLSI circuits at various levels of abstraction; design, layout and computer simulation of circuits; high-level synthesis; design projects.
No. of Wks. | Topics |
---|---|
1 | CMOS Circuits |
2 | Switch level logic simulation using IRSIM |
1 | CMOS device characteristics; CMOS process technology |
1 | CMOS layout using MAGIC |
2 | First-order timing models; Transistor sizing |
1 | CMOS storage elements; Clocked circuits: Dynamic logic |
1 | Hardware Description Languages; Verilog |
1 | CMOS sub-system examples |
Lab Assignments & Homeworks |
20% |
---|---|
Design Projects | 30% |
Midterm | 20% |
Final | 30% |