Computer Aided Design and Analysis of VLSI Circuits - CIS 778

Autumn Quarter 1998 MWF 12:30 - 1:18 (DL 264)

Instructor:  P. Sadayappan (Saday)  Grader:  Raviraj Bhide
Office:  595 Dreese  Office:  Caldwell 408

Phone: 292-0053

Email:  saday@cis.ohio-state.edu Email:  bhide@cis.ohio-state.edu

Office Hours:  MWF 1:30-2:18  Office Hours:  TR 2-3

Catalog Description VLSI design methodology; specification of VLSI circuits at various levels of abstraction; design, layout and computer simulation of circuits; high-level synthesis; design projects.

Course Objectives Upon completing the course, the student will:

• have an understanding of CMOS digital VLSI design principles

• be knowledgeable in the use of CAD tools for the design and verification of digital VLSI circuits

• be able to design a digital system, starting from a high-level description to develop a VLSI layout specification for the circuit

\underline{Prerequisites:} CIS 560; EE 561; and CIS 675 or EE 562

\underline{Text} (Recommended, but not required; two copies will be placed on closed reserve in SEL) Principles of CMOS VLSI Design - A Systems Perspective, 2nd Edition, by Neil Weste and Kamran Eshraghian, Addison Wesley, 1993.

\underline{Grading}

Laboratory Assignments and Homework 20%
Design Projects  30% (15% + 15%)
Midterm (Wed. Oct. 21)  20%
Final (Mon, Dec 7, 11:30 - 1:18)  30%

Policy on Assignments • All assignments are due at the beginning of class on the due date

• Late assignments will be penalized 10% per calendar day (or part thereof) late.

• Late assignments will not be accepted after solutions are provided.

Course Content

\underline{Sequence}  \underline{Topic}

1 CMOS circuits (Ch. 1, Handout) 2 Switch-level logic simulation using IRSIM (Handout) 3 CMOS device characteristics; CMOS process technology (Ch. 2,3) 4 CMOS layout using MAGIC (Handout) 5 First-order timing models; Transistor sizing (Ch. 4,5) 6 CMOS storage elements; Clocked circuits; Dynamic logic (Ch. 5) 7 Hardware description languages; Verilog (Ch. 6, Online Documentation) 8 CMOS sub-system examples (Ch. 8)