CIS 775: Computer Architecture

Spring 1998

Instructor: Dr. D. K. Panda Office: DL 785 Tel: 2-5199 E-mail:panda@cis.ohio-state.edu Office Hours: MW 11:30-1:30, F 11:30-12:30

Grader: Dr. Hyuk Soo Jang Office: DL 493 Tel: 2-2565 E-mail: jang-h@cis.ohio-state.edu Office Hours: Tue, Thurs: 2:30-3:30 pm, Wed 3:30-5:30 pm

Class Hours: MWF 2:30-3:18 pm

Prerequisites: CIS 675 and CIS 660

Syllabus: Fundamentals of Computer Design, Performance Measures, Instruction set Design, Reduced Instruction Set Architecture (RISC), Introduction to Pipelining, Advanced Pipelining Techniques, Memory Hierarchy and Cache Design, Storage Systems, Introduction to Vector and Parallel Computer Architectures.

Objectives:

1. To understand and appreciate the principles and tradeoffs (cost/performance, speed/flexibility) behind the design of modern computer systems in a qualitative and quantitative fashion.

2. To understand issues in choosing and designing an instruction set.

3. To learn the concepts of basic pipelining and advanced pipelining techniques.

4. To learn issues related to hierarchical memory system design.

5. To obtain an overview of vector and parallel computer architectures.

Text Book: Computer Architecture A Quantitative Approach by John Hennessy and David Patterson, Morgan Kauffman, 1996 (second edition).

Grading:

Homeworks (four): 20 % (5.0+5.0+5.0+5.0) Simulation Labs (three): 20 % (3+12+5) Midterm : 25 % Final: 35 %

Homeworks: There will be four problem sets. Due dates (tentative) are mentioned in the class schedule. The problem sets will be distributed before one week of the due date. Late homeworks are not encouraged. An exception to this rule requires that you have a strong and convincing reason. If you have such a reason, you will have to let me know about it in advance. Homework solutions will be distributed in class on the due date/the first class after the due date. Absolutely, no homeworks will be accepted after the solutions are distributed.

Labs using Simulators: There will be three labs involving simulation experiments. The first two labs will be using DLX simulator dlxsim to evaluate instruction statistics, pipelining techniques and branch mechanisms. The first lab will expose you to the dlxsim simulator. The Dinero simulator will be used in the third lab to evaluate different cache organizations. The labs will be distributed around 10 days in advance. Both the simulators are UNIX based and run on the CIS HP network. The labs need to be done individually. Each student has been assigned an account in the CIS network to carry out these simulation. If you do not have an account please let me know about it.

If you are interested in getting familiarized with these simulator environments earlier, you can refer to the respective man pages in /usr/class/cis775/man directory. Manual pages for DLX simulator are available in both postscript (file dlxsim.ps) and L^{A}TEXdvi (file report.dvi) format. You can view the postscript file using ‘ghostview’ command and the dvi file using ‘xdvi’ command. Similarly, the man page for Dinero is available as an ascii dinero.cat file in this directory. The corresponding programs (dlxcc for generating assembly code from a C program, dlxsim for executing the assembly program on DLX processor, and dinero to study the impact of cache organizations) can be invoked from /usr/class/cis775/hp/bin directory. Detailed guidelines to carry out these labs will be provided with the homeworks and lab handouts.

Examinations: There will be two examinations. A midterm will be held on the sixteenth class and a final at the end of the quarter, as indicated below. Examinations are closed book, closed notes, and closed neighbors.

MIDTERM  Monday May 4  2:30pm – 3:18pm in class

FINAL (Regular) Tuesday June 9 11:30am – 1:18pm in class FINAL (Graduating Seniors) Wednesday June 3 2:30pm – 4:30pm TBD

Electronic Distribution of Class Materials: During the first week of the class, I will collect e-mail addresses of all students to create an electronic mailing list. Make sure that you give me your e-mail address (campus or work) on the system you frequently log on. If you do not receive any e-mail from me by the second week of the class, please check with me to ensure that your name is in the mailing list. I will use this mailing list throughout the quarter to make important announcements and clarifications about homework problems, if needed.

All homeworks will be made available (postscript versions) through the Web. The URL is

http://www.cis.ohio-state.edu/~panda/775. An e-mail announcement will be made when

each homework is placed on the Web.

Tentative Class Schedule

Week Topics

Readings from Text

Mar 30 Introduction; Course Overview Technology Trends 1.1–1.3 Cost and Performance 1.4–1.5 Quantitative Principles of Computer Design 1.6 Reading Assignment 1.7–1.9

Apr 6  Classifying Instruction Set Architectures  2.1–2.2

Features of Instruction Set 2.3–2.6 DLX Architecture 2.8 Reading Assignment 2.7,2.9–2.10

Apr 13  Basic Pipelining and Hazards  3.1–3.3

Hw#1 due (Apr 13)

Apr 20  Data Hazards  3.4

Control Hazards 3.5 Lab#1 due (Apr 20)

Apr 27  Interrupts and Exceptions  3.6

Multicycle Operations 3.7 Crosscutting Issues in Pipelining 3.8 Reading Assignment 3.9–3.10 Hw#2 due (Apr 29)

May 4 MIDTERM (May 4)

Instructional-Level Parallelism 4.1 Dynamic Scheduling 4.2

May 11  Dynamic Scheduling (Contd.)  4.2

Memory-Hierarchy Design and Caches 5.1–5.2 Reducing Cache Misses 5.3 Lab#2 due (May 11)

May 18  Reducing Cache Miss Penalty and Hit Time  5.4–5.5

Main Memory Design Issues 5.6 Crosscutting Issues 5.9 Reading Assignment 5.10 Hw#3 due (May 20)

May 25  Vector Processors  B.1–B.3

Lab#3 due (May 29)

June 1  Vector Processor Performance  B.4–B.5

Overview of Interconnection Networks 7.1–7.5 Overview of Multiprocessors 8.1–8.4 Course Review Hw#4 due (June 3, graduating seniors; June 5, regular) Graduating Seniors FINAL (June 3) Regular FINAL (June 9)