CIS 775: Computer Architecture

CIS 775: Computer Architecture

Description

Fundamentals of Computer Design, Performance Measures, Instruction set Design, Reduced Instruction Set Architecture (RISC), Introduction to Pipelining, Advanced Pipelining Techniques, Memory Hierarchy and Cache Design, Storage Systems, Introduction to Vector and Parallel Computer Architectures.*
*The description in the published catalog is outdated; this revised description will appear in future catalogs.

Level, Credits, Class Time Distribution

UG 3 (three hour lectures)

Prerequisites

CIS 660; CIS 675 or EE 562.

Quarters Offered

Au, Sp

General Information, Exclusions, etc.

None.

Objectives

Mastery of the principles and tradeoffs (cost/performance, speed/flexibility) behind the design of modern computer systems in a qualitative and quantitative fashion.
Mastery of issues in choosing and designing an instruction set.
Mastery of the concepts of basic pipelining and advanced pipelining techniques.
Mastery of issues related to hierarchical memory system design.
Familiarity with vector and parallel computer architectures.

Texts

Computer Architecture A Quantitative Approach by John Hennessy and David Patterson, Morgan Kauffman, 1996 (second edition).

Relationship to ABET Criterion 3

Relationship to CSE Program Objectives

a	b	c	d	e	f	g	h	i	j	k
XX	X	X		XX	X			X		XX

1a	1b	1c	2a	2b	3a	3b	3c	4a	4b
XXX	XX	XX					X	XXX	XXX

Topics

No. of Wks.	Topics
1	Introduction; Course overview; Technology trends; Cost and performance; Quantitative principles of computer design.
1	Classifying Instruction Set ARchitectures; Features of an Instruction Set; DLX Architecture.
1	Basic pipilining and hazards.
1	Data hazards, Control hazards.
1	Interrupts and Exceptions; Multicycle operations; crosscutting issues in Pipelining;.
1	Instruction level parallelism; Dynamic scheduling
1	Memory-Hierarchy Design and Caches; Reducing Cache misses.
1	Reducing Cache miss penalty and Hit time; Main memory design issues; Crosscutting issues
1	Vector Processors
1	Vector Processor performance; Overview of Interconnection Networks; Overview of Multiprocessors. Course Review.

Homeworks and Lab Assignments (Representative)

There will be four homeworks and three lab assignments. The first two labs will use the DLX simulator, the third lab will use the Dinero simulator.

Grading Plan

Homeworks	20%
Labs	20%
Midterm	25%
Final	35%

Prepared By

D. Panda (Date: March 30, 1999).