Computer Architecture Course Group Report

June 2009

(This report is available at: http://www.cse.ohio-state.edu/~teodores/download/misc/architecture2009.html. This report adopts a new structure compared to previous CGRs following to the new guidelines set forth by the Curriculum Committee.

Architecture Courses

Course no. Title Credit 
Hours		 Reqd - Core (R)/
Reqd - Option (O)/
Elective (E)		 Capstone?
CSE 360
Introduction to Computer Systems
4
R
no
CSE 621
Introduction to High-Performance Computing
3
O
no
CSE 675.01
Introduction to Computer Architecture
3
R
no
CSE 675.02
Introduction to Computer Architecture
3
R (CIS only)
no
CSE 676
Computer Systems and Interfaces
3
O
no
CSE 721
Introduction to Parallel Computing
3
E
no
CSE 775
Computer Architecture
3
E
no
CSE 778
Computer-Aided Design and Analysis of VLSI
4
E
yes
CSE 875
Advanced Computer Architecture
3
E
no
ECE 206
Switching Circuits Laboratory
1
R
no
ECE 261
Introduction to Logic Design
3
R
no
ECE 300
Electrical Circuits
3
R
no
ECE 309
Electrical Circuits Laboratory
1
R
no
ECE 320
Electronic Devices and Controls
3
R
no
ECE 567
Microprocessor Laboratory
2
R
no

1. Summary

The core of the Computer Architecture Course Group consists of CSE 360 and CSE 675.01. CSE 360 introduces the student to the internal representation of programs in a computer and the fundamental Von Neumann machine model. CSE 675.02 provides detail on the architecture of a computer. ECE 261 and ECE 206 provide a background in logic design and serve as pre-requisites to CSE 675.01. ECE 300, 309, and 320 provide an introduction analog circuits and devices. ECE 567 provides hands-on experience with microprocessor-based systems. CSE 676 is required for the Hardware/Software option, providing greater depth on microprocessors and hardware interfaces.

The electives in this group include CSE 775, the graduate level architecture course that builds on the fundamentals from CSE 675; CSE 778, which is a Capstone course, that allows a student to develop a deeper understanding of how digital chips are designed and implemented in VLSI; CSE 621 and 721, that focus on aspects of high-performance and parallel computing.

This document is organized as follows: Section 2 provides a detailed analysis of the courses included in the Architecture Group. Section 2.1 describes the individual courses and their relations to the other courses in the group as well as to the rest of the curriculum. Section 2.2 contains an evaluation based on intended learning outcomes (LOs). Section 2.3 considers the relation between the LOs of the various courses and the BS-CSE program outcomes. Section 3 provides information on the feedback we have received about the courses in the group as well as changes made since our last report. Section 4 concludes.

2. Detailed Analysis

2.1 Summary of the courses

CSE 360: This is a four-credit course that serves as the introduction to computer architecture as well as a low-level programming class. The class meets for 4 lecture hours/week.

This course is the students' first exposure to how a computer actually works. It approaches the material at the level just above the actual electronic components of the machine. The course starts with binary encoding of integers (2's complement), characters (ASCII), strings, and hexadecimal notation. It continues with a brief introduction to logic gates and provides an intuition of how gates can be used to form simple combinatorial and sequential circuits (CSE 675 expands on this material). The course introduces binary encoding of data and instructions, covering machine instruction representation and how assembly instructions relate to each other. The students become familiar with components (e.g., registers) which make up a CPU and CPU control at the register-transfer level. They also become familiar with assembly programming including the use of pointers and subroutine linkage using stacks. At the end of the course, they are exposed to interrupts, interrupt handlers, operating system service routines, and DMA control.

CSE 621: This is a course that explores performance issues in computing. The objectives of the course are to present the principles of development of efficient software for computers (from modern engineering workstations to highly parallel supercomputers), and to provide education in the effective use of these machines for scientific and engineering computations. Topics include high-performance architectures; shared-memory and message-passing models for parallel programming; design, analysis, implementation and performance evaluation of parallel algorithms. Laboratory exercises involve implementation and performance evaluation on a number of architectural platforms.

CSE 675: The second course in the sequence is CSE 675, Introduction to Computer Architecture. This course exposes the students to the following concepts: computer system components, instruction set design, integer arithmetic algorithms/circuits, floating point arithmetic algorithms/circuits, datapath design, hardwired control units, programmable control units, and introduction memory and I/O interfaces. The students get exposed to RISC processors in this courses. The course has two versions, 675.01 (3 credits) and 675.02 (4 credits); the former is taken by CSE majors who have background in logic design (having taken ECE 261 and 206), the latter is for CSE majors who do not have the logic design background.

CSE 676: This course, Computer Systems and Interfaces, is an elective course for students specializing in hardware/software systems. The following topics are covered: operational principles of computer systems and interfaces, software and hardware interface issues, protected mode operations, interrupt handling, input/output, bus structures and standards, interfacing issues with memory, DMA, disk, display, and network. In this course students get exposed to the PC architecture and interfacing issues.

CSE 721: This course presents the principles and practice of parallel computing. The design, implementation and evaluation of parallel programs for shared-memory and distributed-memory architectures are discussed. Efficient parallel algorithms for a number of numeric and non-numeric applications are studied. Laboratory exercises are conducted on parallel and distributed computing systems.

CSE 775: This is the third course in the architecture sequence. It is primarily a graduate-level course and is taken by some undergraduate students as an elective. The topics in this course are: fundamentals of computer design, performance measures, instruction set design, reduced instruction set architecture (RISC), pipelining, memory hierarchy and cache design, vector, parallel and multicore architectures. The students also perform simulation-based design to get an in-depth understanding of pipelined design and memory hierarchy.

CSE 778: This is a capstone course recommended for BS CSE majors following the hardware/software option. It covers the design and analysis of digital VLSI circuits. Both low-level custom and VLSI layout at the transistor level, as well as high-level design using the hardware description language (HDL) Verilog are explored in detail. Students carry out design projects at both levels. The course places a strong emphasis on developing communication skills and encouraging teamwork. Students are encouraged to work in teams of three or four rather than individually. This allows them to learn from and build on each other's technical skills leading to better designs, but also help each other's communication abilities. Every student is also required to participate in oral presentations.

CSE 875: This is the final course in the architecture sequence. This is a graduate-level course and discusses the following concepts: convergence of parallel architectures and fundamental design issues, design of shared-memory multiprocessors, Snoop-based multiprocessors, designing scalable multiprocessors and scalable DSM systems with directory-based cache coherence, interconnection network design principles, routine algorithms, collective communication support, network architectures and messaging layers, and future directions in architecture.

ECE 206, 261, 567: These three courses, required of all CSE majors, provide hands-on circuit-level and chip-level understanding and intuition concerning the various components discussed in the other architecture courses. They also allow CSE majors to work with ECE majors. ECE 206 covers the basics of logic design, including NAND, NOR, XOR gates; combinational circuits; adders; code converters; flip flops; sequential circuits; shift registers. ECE 261 gives an introduction to combinational switching theory, Boolean algebra, and clocked sequential networks. ECE 567 is a Laboratory in which the concept of a microprocessor/microcontroller is explored by designing and building simple systems using in-circuit development tools.

ECE 300, 309, 320: These courses, also required of all CSE majors, are more concerned with analog circuits and hence do not directly involve architecture issues. Nevertheless, they do add to the general circuit-level intuitions and knowledge of the students; and they also allow CSE majors to work with students in other majors. ECE 300 gives an introduction to circuit analysis, circuit analysis concepts and their extension to mechanical and thermal systems. It also gives some background on electrical instruments and measurements. ECE 309 accompanies and complements ECE 300 by demonstrating the physical principles discussed there; use of electrical instruments such as oscilloscopes, voltmeters, ammeters, etc., are also emphasized. ECE 320 focuses on the theory and applications of electronic devices, control circuits, feedback and operational amplifiers.

2.1.1 Relation to the rest of the CSE program

CSE 360 is required of all students (both CSE majors and CSE majors). The course is usually taken immediately after students have completed the software spine (CSE 221, 222, 321); some students take it concurrently with CSE 222. Students pursuing a minor in CSE and following the Programming and Algorithms track are also required to take the course. CSE 360 is a prerequisite for the keystone system software design course (CSE 560) as well as CSE 675.

CSE 675 is required of all CSE majors and all BS CIS majors (for BA CIS majors, it is an elective). Math 366 and CSE 360 (or ECE 265) are prerequisites for the course. CSE 675.01 also has ECE 261 as a prerequisite. This course is a prerequisite for CSE 660 and CSE 775.

CSE 676 is required of BS CSE majors in the Hardware/Software option and is an elective for other majors.

ECE 206, 261, 567, as noted above, primarily serve to provide circuit-level and chip-level understanding of architecture issues discussed in CSE 360, 675, etc.

With respect to the other courses, CSE 675 is a prerequisite for CSE 775 which in turn is a prerequisite for CSE 875. CSE 541 (Numerical Methods) and Math 568/571/601 (Linear Algebra) are prerequisites for CSE 621 which in turn is a prerequisite for CSE 721.

In summary, the courses in this group provide students with a solid grounding in principles and concepts of computer architecture. There are some important connections between the courses in this group, in particular CSE 360 and 675, and other courses such as CSE 560, 655, 660, etc.; these connections enable students to see how architecture concepts influence and are in turn influenced by developments and ideas in other parts of Computer Science.

2.2 Evaluation of courses

Note: The syllabus of each course lists a set of intended learning outcomes (LOs). Each LO specifies an item of knowledge and/or skill at one of three levels of performance, mastery, familiarity, or exposure. Mastery means the student should be able to apply the knowledge or skill even in a new context, and even when not specifically instructed to do so; familiarity means the student will be able to apply it even in a new context, when instructed to do so; and exposure means the student will have heard the term and/or seen it used, but may not be able to discuss or use it effectively without further instruction.

CSE 360 The learning outcomes of this course are to:

LO1: Students are introduced to four architectures: Sparc, MIPS, a theoretical machine named SAM and a CISC architecture (M68HC11). They learn to distinguish between RISC and CISC, identify load/store, 1-, 2-, 3- address instruction architecture and understand the implications of pipelining.

LO2: Students learn several integer encoding schemes, such as signed magnitude, BCD, simply binary and two's complement. They also learn ASCII and are introduced to Unicode and EBCDIC. During the section on addressing modes, students develop strategies for managing records and linked lists. During the section on subroutines, students learn to create and manage stack structures.

LO3: Students learn RTL for a theoretical machine (SAM) and through many assignments, use it to describe the implementation of new machine instructions on that architecture.

LO4: Students learn to encode and decode instructions for the SAM theoretical machine, as well as the Sparc and HC11 architectures.

LO5: In a three day unit, students are introduced to the concepts of isolated I/O, programmed I/O, interrupts, exceptions, external operations and traps.

LO6 and LO7: Students learn two subroutine linkage conventions: register-based parameter passing and stack-based parameter passing.

LO8: Students are required to read and interpret individual instructions and programs for the M68HC11 CISC architecture.

CSE 621 The learning outcomes of this course are to:

The effect of cache, instruction-level parallelism and vector instructions on achieved performance on modern processors are emphasized via lecture material and laboratory exercises to reinforce LO1. Loop transformations such as permutation, unrolling, tiling and fusion along with laboratory exercises help achieve LO2. OpenMP, Pthreads, and MPI are covered along with laboratory exercises to attain LO3. Lecture material and laboratory exercises requiring performance prediction and measurement are used to achieve LO4.

CSE 675 This course has two versions, 675.01 (3 credits) and 675.02 (4 credits); the former is taken by CSE majors who have background in logic design (having taken ECE 261 and 206), the latter is for CIS majors who do not have the logic design background.

The learning outcomes for 675.01 are to:

The learning outcomes for 675.02 are to:

LO1 is achieved by focusing several lectures on the various tradeoffs involved in designing a computer system. Students are exposed to the most important factors affecting both cost and performance and are able to solve problems that ask them to make the best design choices.

LO2 is achieved mainly in the first half of this course as various hardware components are introduced. These components are put together in the second half of the class to design a processor datapath. This achieves LO3.

The class uses the MIPS instruction set architecture. Some of the design tradeoffs of the MIPS ISA are discussed and a comparison with CISC design tradeoffs is made. This provides students with some familiarity with the ISA design process (LO4).

The last part of the class focuses on the memory hierarchy with a special focus on the cache subsystem. The students only reach familiarity with LO5 because of the limited time that can be spent on the subject.

675.02 also gives students background on logic design. LO6 is achieved at the familiarity level although this sometimes requires spending more time than budgeted for that chapter.

Based on the results of the POCAT exams given in the past few years CSE 675 is doing very well. In the latest exam (SP09) 70% of the students answered the question on CSE 675 correctly.

CSE 676 The learning outcomes of this course are to:

All the learning outcomes listed are being achieved at the specified levels.

CSE 721 The learning outcomes of this course are to:

The following was removed from LO5: "such as, Cray T94, SGI Origin 2000, and cluster of PCs". The machines used in this course have been updated to reflect more current architectures.

Concepts learned in CSE 621 are reinforced to achieve LO1 through a more in-depth coverage on performance modeling for communication (point-to-point and collective) for different interconnection topologies. LO2 and LO3 are achieved through study of parallel algorithms for numerical algorithms (dense and sparse linear algebra, FFT) as well as non-numerical algorithms (e.g. sorting). Coverage of multi-core architectures and GPUs along with laboratory exercises helps achieve LO4 and LO5.

CSE 775 The learning outcomes of this course are to:

Students get in-depth coverage on quantitative and qualitative issues in designing modern processors. They also get in-depth coverage on design principles for instruction set architectures and pipelining (basic and advanced) techniques. They get exposed to instructional level parallelism. They also get exposed to the design of memory hierarchy including multi-level caches. Thus, all the learning outcomes listed are being achieved at the specified levels. A new LO has been added: L04 is "Be familiar with instruction level parallelism".

CSE 778 The learning outcomes of this course are to:

LO1 is achieved by learning restoring logic and transmission logic design styles, switch level simulation, first order timing models for CMOS circuits (LO4). LO2 and LO3 are achieved by learning use of a CMOS layout design tool, extraction and switch level simulation for functional and timing verification, and the Verilog language. One layout-level design project and another Verilog design project (requiring use of both behavioral as well as structural design) are used to achieve LO3. Teamwork and written/oral communication skills are emphasized through team projects. A term paper on VLSI technology trends reinforces LO5.

CSE 875 The learning outcomes of this course are to:

Students get in-depth coverage on understanding the principles of advanced computer architecture and hardware parallelism. They get in-depth coverage on designing various types of parallel systems (shared memory with coherency, distributed memory and massively parallel systems). Principles of interconnection networks to design various kinds of scalable systems are focused. Trends (past, present and future) for computing platforms (including multi-core processors) and interconnection networks are focused. Relationship between parallel architectures, programming models and parallel applications are stressed. Thus, all the learning outcomes listed are being achieved at the specified levels.

2.3 Relation to BS-CSE program outcomes (POs) and evaluation

The (proposed) new program outcomes are to:
  1. an ability to apply knowledge of computing, mathematics including discrete mathematics as well as probability and statistics, science, and engineering;
  2. an ability to design and conduct experiments, as well as to analyze and interpret data;
  3. an ability to design, implement, and evaluate a software or a software/hardware system, component, or process to meet desired needs within realistic constraints such as memory, runtime efficiency, as well as appropriate constraints related to economic, environmental, social, political, ethical, health and safety, manufacturability, and sustainability considerations;
  4. an ability to function effectively on multi-disciplinary teams;
  5. an ability to identify, formulate, and solve engineering problems;
  6. an understanding of professional, ethical, legal, security and social issues and responsibilities;
  7. an ability to communicate effectively with a range of audiences;
  8. an ability to analyze the local and global impact of computing on individuals, organizations, and society;
  9. a recognition of the need for, and an ability to engage in life-long learning and continuing professional development;
  10. a knowledge of contemporary issues;
  11. an ability to use the techniques, skills, and modern tools necessary for practice as a CSE professional.
  12. an ability to analyze a problem, and identify and define the computing requirements appropriate to its solution;
  13. an ability to apply mathematical foundations, algorithmic principles, and computer science theory in the modeling and design of computer-based systems in a way that demonstrates comprehension of the tradeoffs involved in design choices;
  14. an ability to apply design and development principles in the construction of software systems of varying complexity.

CSE 360 The learning outcomes of this course are to:

Learning
Outcome 		Relation to BS-CSE Program Outcomes
(a) (b) (c) (d) (e) (f) (g) (h) (i) (j) (k) (l) (m) (n)
LO1 X XXX XXX   XX X   X X   XX      
LO2 XX XXX XXX   XX X   X X   X      
LO3 XX   XXX   XX X   X X   XX      
LO4 XX X     XX X   X X   XX      
LO5                            
LO6 XX XXX X   XX X   X X   XX      
LO7 X X     XX X   X X   XX      
LO8 X       XX X   X X   XX      
LO9 X       XX X   X X   XX      

CSE 621 The learning outcomes of this course are to:

Learning
Outcome 		Relation to BS-CSE Program Outcomes
(a) (b) (c) (d) (e) (f) (g) (h) (i) (j) (k) (l) (m) (n)
LO1 XXX   X           X       XX  
LO2 XX XX X   X           XX      
LO3     XX           X X XX XX   XX
LO4   XX XX X XX X   X     XX XX XX XX

CSE 675.01 The learning outcomes for this course are to:

Learning
Outcome 		Relation to BS-CSE Program Outcomes
(a) (b) (c) (d) (e) (f) (g) (h) (i) (j) (k) (l) (m) (n)
LO1 XX XX XXX   XX X   X X X XX XXX XX X
LO2 X XXX XXX   XX X   X X X XX XX X  
LO3 XX XXX XXX   XX X   X X X XX XX X X
LO4   XXX XXX   X           XX      
LO5   XXX XXX   X         X XX      

Based on the results of the POCAT exams given in the past few years CSE 675 is doing very well. In the latest exam (SP09) 70% of the students answered the question on CSE 675 correctly.

CSE 675.02 The learning outcomes for this course are to:

Learning
Outcome 		Relation to BS-CSE Program Outcomes
(a) (b) (c) (d) (e) (f) (g) (h) (i) (j) (k) (l) (m) (n)
LO1 XX XXX XXX   XX X   X X X XX XXX XX X
LO2 X XXX XXX   XX X   X X X XX XX X  
LO3 XX XXX XXX   XX X   X X X XX XX X X
LO4   XXX XXX   X           XX      
LO5   XXX XXX   X         X XX      
LO6   XX XXX   X           XX      

CSE 676 The learning outcomes of this course are to:

Learning
Outcome 		Relation to BS-CSE Program Outcomes
(a) (b) (c) (d) (e) (f) (g) (h) (i) (j) (k) (l) (m) (n)
LO1 XX XX XX   XXX X     X   XX XX XX X
LO2 XX XX X   XX X     X   XX XX XX X
LO3 X X XX   X X     X   XX X X X
LO4 XX X X   XX X     X   XX X XX X
LO5 X XX XX   X X     X   XX XX X X

CSE 721 The learning outcomes of this course are to:

Learning
Outcome 		Relation to BS-CSE Program Outcomes
(a) (b) (c) (d) (e) (f) (g) (h) (i) (j) (k) (l) (m) (n)
LO1 XX XXX XXX   XX       X   XXX XXX XXX XXX
LO2 XXX XXX XXX   XX       X   XXX XXX XXX XXX
LO3 XXX XXX XXX X XXX X     X   XXX XXX XXX XXX
LO4   XXX XXX X XXX X     X          
LO5 X   X   X       X     X    

CSE 775 The learning outcomes of this course are to:

Learning
Outcome 		Relation to BS-CSE Program Outcomes
(a) (b) (c) (d) (e) (f) (g) (h) (i) (j) (k) (l) (m) (n)
LO1 X XXX XXX   XXX X     X   XX XX X XX
LO2 X XXX XXX   XXX X     X   XX XX X XX
LO3 X XXX XXX   XXX       X   XX XX X XX
LO4 X XXX XXX   XXX       X   XX XX X XX
LO5 X XXX XXX   XXX X     X   XX XX X XX

CSE 778 The learning outcomes of this course are to:

Learning
Outcome 		Relation to BS-CSE Program Outcomes
(a) (b) (c) (d) (e) (f) (g) (h) (i) (j) (k) (l) (m) (n)
LO1 XXX X XXX   X         XX XXX XX XX  
LO2 XX XXX XXX XX XX   XX     XX XXX XXX   XX
LO3 XX XXX XXX XXX XXX XX XXX XX XXX XX XXX XXX XXX XXX
LO4 XXX XXX X   XX           XX XX XX  
LO5         X     X XX XXX XX      

CSE 875 The learning outcomes of this course are to:

Learning
Outcome 		Relation to BS-CSE Program Outcomes
(a) (b) (c) (d) (e) (f) (g) (h) (i) (j) (k) (l) (m) (n)
LO1 X XXX XXX   XXX X     X   XX XX X XX
LO2 X XXX XXX   XXX X     X   XX XX X XX
LO3 X XXX XXX   XXX X     X   XX XX X XX
LO4 X XXX XXX   XXX X     X   XX XX X XX
LO5 X XXX XXX   XXX X     X   XX XX X XX
LO6 X XXX XXX   XXX X     X   XX XX X XX

3. Feedback and changes

The principal vehicles for feedback about our courses have been the standard SETs in individual courses and direct instructor feedback. These have generally been positive. We are also evaluating the results of the POCAT exams. The questions in the POCAT are based on high-level required courses and are useful in evaluating courses like 675.

3.1 Changes since our last report

As discussed in our last report, CSE 778 was revised to better serve as a capstone design course. The communications component was strengthened by requiring every student to make oral presentations. The team working component was strengthened by having the students work on the design projects in teams of three or four rather than individually. This has enabled students to learn from and build on each other's technical skills leading to better designs and overall to a better capstone course.

Another concern expressed in the previous report was that CSE 360 focused on a different architecture than the one used in ECE 265 (HC11). CSE majors have complained that, as a result, they find themselves at a disadvantage compared with ECE majors when they take ECE 567 since that course is based on HC11. This concern was addressed by adding three hours on the HC11 architecture to CSE 360. Students are now able to answer questions on the organization of the HC11 architecture (registers, CCR, etc), read and interpret the effects of HC11 instructions. This material forms the basis of one of the homework assignments and there is a problem on the final exam that is worth 10% of the points.

3.2 Future directions

Multi-core architectures are becoming significantly important. Currently, 775 provides a broad overview of this emerging trend. More details are covered in 875. Since multi-core architecture will be a dominant trend for the coming years, we plan to increase the coverage of multi-core architecture in both 775 and 875. For example, 2-3 classes in 775 can be used to cover the challenges and designs of latest multi-core processors. In 875, around two weeks can be used to cover multiple aspects of multi-core designs (such as on-chip interconnection, multi-level caches and their impact at sockets-level, node-level and systems-level).

The switch to semesters will require a major re-evaluation and redesign off all the courses in the architecture group. We are not planning any other changes to the course structure before this major revision.

4. Conclusions

The Computer Architecture Group is a key part of the CSE program and helps us meet a number of objectives of the CSE program. The required courses in the group provide students with essential knowledge and intuition concerning how computers work at the hardware level and how standard system-level software works. The elective courses equip interested students with more advanced and more detailed knowledge of current machines as well as an appreciation of how architecture has evolved over the years, and allow them to engage in design projects using standard industry practices and tools. All of this prepares them for both advanced study as well as for professional careers. The courses, as they stand, are doing reasonably well. No major changes are planned before the semester transition.
 
Course no. Coordinator Recent Instructors
CSE 360 Bair Bair, Heym, Parent
CSE 621 Sadayappan Sadayappan
CSE 675 Teodorescu Babic, Teodorescu
CSE 676 Babic Liu, Panda
CSE 721 Sadayappan Sadayappan
CSE 775 Panda Panda
CSE 778 Sadayappan Sadayappan
CSE 875 Panda Panda

People involved in preparing report: Teodorescu, Panda, Sadayappan, Parthasarathy, Babic, Heym, Bair.

Date of report: June 2009