Analysis of commercial workload on SMP multiprocessors 

X. Zhang, Z. Zhu, and X. Du      

Proceedings of Performance'99, August, 1999, pp. 331-346.  
 
Abstract
--------

A major challenge of studying architectural effects on the performance
of a commercial workload is the lack of easy access to large scale
and complex database engines running on a multiprocessor system with
powerful I/O facilities. Experiments involving case studies have
been shown to be highly time-consuming and expensive.  We present an
analytical model to address this issue.  Our model characterizes both
the memory access patterns of a commercial workload and the memory
hierarchy of SMP multiprocessors.  We use the commercial benchmark TPC-C
as the workload. The model is able to predict the execution time of the
workload, the number of cycles per instructions (CPI), and transaction
throughput on SMPs. We have validated the model using the published
performance results of TPC-C workload measured by hardware counters on a
Pentium Pro-based SMP server.  We have also validated the model by running
TPC-C workload on a simulated SMP by SimOS.  Our study demonstrates that
this modeling approach is a feasible, cost-effective, and accurate way
to evaluate the performance of a commercial workload on SMPs, and is
complementary to the measurement-based experimental approaches.