TR-10-3.pdf

"PS-BC: power-saving considerations in design of buffer caches serving 
heterogeneous storage devices"

Feng Chen and Xiaodong Zhang

Proceedings of 16th ACM International Symposium on Low Power Electronics and 
Design (ISLPED 2010), Austin, Texas, August 18-20, 2010.


Abstract

Under a replacement policy, existing operating systems identify
and maintain most frequently used storage data in buffer
caches located in main memory, aiming at low-latency I/O
data accesses. However, replacement policies can also strongly
affect energy consumptions of various connected storage devices,
which has not been a consideration in the design and
implementation of buffer cache management. In this paper,
we present a system framework for an energy-aware
buffer cache replacement, called PS-BC (power-saving buffer
cache). By considering several critical factors affecting system
energy consumption, PS-BC can effectively improve system
energy efficiency, while it is able to flexibly incorporate
conventional performance-oriented buffer cache replacement
policies for different performance objectives. Our experimental
studies based on a trace-driven simulation show that
the PS-BC framework embedded with the CLOCK replacement
policy can achieve an energy saving rate of up to 32.5%
with a minimal overhead for various workloads.

Back to the Publication Page.

Back to the HPCS Main Page at the Ohio State University.