Breaking address mapping symmetry at multi-levels of memory hierarchy to 
reduce DRAM row-buffer conflicts 

Zhao Zhang, Zhichun Zhu, and Xiaodong Zhang

Journal of Instruction-Level Parallelism, Vol. 3, 2001.

Abstract

DRAM row-buffers have become a critical level of cache in the memory hierarchy 
to exploit spatial locality in the cache miss stream. Row-buffer conflicts 
occur when a sequence of requests on different pages goes to the same memory 
bank, causing higher memory access latency than requests to the same row 
or to different banks. In this paper, we first show that the address mapping 
symmetry between the cache and DRAM is the inherent source of row-buffer 
conflicts. Breaking the symmetry to reduce the conflicts and to retain the 
spatial locality, we propose and evaluate a permutation-based page 
interleaving scheme. We have also evaluated and compared two representative 
cache mapping schemes that break the symmetry at the cache level. We show 
that the proposed page interleaving scheme outperforms all other mapping 
schemes based its overall performance and on its implementation simplicity. 

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