A Permutation-based Page Interleaving Scheme to Reduce 
Row-Buffer Conflicts and Exploit Data Locality

Z. Zhang, Z. Zhu, and X. Zhang 

Proceedings of the 33rd Annual International Symposium on Microarchitecture, 
(Micro-33), Monterey, California, December 10-13, 2000, pp. 32-41. 

Abstract 

DRAM row-buffer conflicts occur when a sequence of requests on different 
rows goes to  the same memory bank, causing much higher memory access 
latency than requests to the same row or to different banks. In this paper, 
we analyze the sources of row-buffer conflicts in the context of superscalar 
processors, and propose a permutation-based page ingterleaving scheme to 
reduce row-buffer conflicts and to exploit data access locality 
in the row buffer. Compared with several existing schemes, we show that 
the permutation-based scheme dramatically increase hit rates on DRAM 
row-buffers and reduces  memory stall time of the SPEC95 and TPC-C workloads. 
The memory stall times of the workloads are reduced up to 68% and 50% 
compared with the conventional cache line and page interleaving schemes, 
reespectively.